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«A Thesis Presented to The Academic Faculty by Scott R. McCann In Partial Fulfillment of the Requirements for the Degree Master's of Science in the ...»

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EXPERIMENTAL AND THEORETICAL ASSESSMENT OF THIN

GLASS PANELS AS INTERPOSERS FOR MICROELECTRONIC

PACKAGES

A Thesis

Presented to

The Academic Faculty

by

Scott R. McCann

In Partial Fulfillment

of the Requirements for the Degree

Master's of Science in the

School of Mechanical Engineering

Georgia Institute of Technology

May 2014

COPYRIGHT 2014 BY SCOTT MCCANN

EXPERIMENTAL AND THEORETICAL ASSESSMENT OF THIN

GLASS PANELS AS INTERPOSERS FOR MICROELECTRONIC

PACKAGES

Approved by:

Dr. Suresh K. Sitaraman, Advisor School of Mechanical Engineering Georgia Institute of Technology Dr. Rao R. Tummala School of Electrical and Computer Engineering and School of Material Science Engineering Georgia Institute of Technology Dr. Yogendra Joshi School of Mechanical Engineering Georgia Institute of Technology Date Approved: April 4, 2014

ACKNOWLEDGEMENTS

There are many people that I need to thank for their time, energy, and support for not only this work, but for helping to get me here.

I would like to thank my advisor, Prof. Suresh Sitaraman, who provided incredible support and guidance throughout my time at Georgia Tech. I would also like to thank Prof. Rao Tummala and Prof. Yogendra Joshi for their valuable time and feedback as committee members.

In addition to being a committee member, I would like to thank Prof. Tummala as the Director of 3D Microsystems Research Center (Packaging Research Center), which provided the industry based motivation for my work. I am in debt to many other members of PRC, including: Makoto Kobayashi, Anne Matting, Vanessa Smet, and Anna Stumpf for assembly work and discussions; Florian Nebe, Ichiro Sato, Yutaka Takagi, and Tao Wang as well as Jason Bishop and Chris White for cleanroom assistance; and Patricia Allen, Karen May, and Brian McGlade for administrative support.

I would like to thank the members of Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab who offer valuable discussion and support every day, including Wei Chen, Justin Chow, Xi Liu, Raphael Okereke, and Christine Taylor. In particular, I would like to thank Sathya Raghavan for modeling support and experimental guidance.

I would like to thank my parents who have provided incredible love, support, guidance, and friendship throughout my life, and without whom, I would not be where I am or who I am today. I would like thank my sister, Katherine, as well asmy extended family.

–  –  –

#1) 25 5.3.2 Shadow Moiré Data for 25mm, 300µm Glass with 10mm, 400µm Die (Sample #2) 35 5.3.3 Shadow Moiré Data for 18.4mm, 150µm Glass with 10mm, 200µm Die

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Table 6.1: Isotropic, temperature-independent material properties.

Table 6.2: Temperature dependence of copper modulus [37].

Table 6.3: Coefficients for Anand’s viscoplastic model of tin silver solder [23].

............ 51 Table 6.4: Sequential fabrication process temperatures.

Table 8.1: Thermal cycling conditions.

Table 8.2: Coffin-Manson coefficient values.

Table 9.1: Stress during fabrication as function of glass thickness.

Table 9.2: Fatigue life for 25mm, 150µm core with 10mm, 200µm die (with underfill).

76

–  –  –

Figure 2.1: Cross-section of ball grid array package (credit: [5])

Figure 4.1: Cross section schematic of fabrication process steps.

From the top, (a) bare glass; (b) polymer laminated glass; (c) interposer with trace pattern; (d) after die assembly (with partially hidden underfill).

Figure 4.2: Glass panel during fabrication: after ZS-100 lamination, hot press, and curing.

Figure 4.3: Mask used for interposer fabrication.

Top image is full interposer layout with die region in center. Regions 1 and 2 are expanded below. The large pads surrounding the die are for test purposes.

Figure 4.4: Glass panel during fabrication: after electroplating copper, before stripping photoresist.

Figure 4.5: Glass panel during fabrication: after etching, before surface finish.

.............. 16 Figure 4.6: Partially diced glass interposer panel, prior to assembly.

Figure 4.7: Temperature profile of thermo-compression bonding

Figure 4.8: Assembled 25 mm x 25 mm x 100 µm glass interposer with 10 mm x 10 mm x 400 µm die (sample #1).

Figure 4.9: Assembled 25 mm x 25 mm x 300 µm glass interposer with 10 mm x 10 mm x 400 µm die (sample #2).

Figure 5.1: TherMoiré PS400TM by akrometrix.

Figure 5.2: Viewing angle: die side and substrate side.

Figure 5.3: Shadow moiré data for 25 mm x 25 mm x 100µm glass with 10 mm x 10 mm x 400µm die (sample #1) at 30 ºC.





–  –  –

x 400µm die (sample #1) at 60 ºC.

Figure 5.5: Shadow moiré data for 25 mm x 25 mm x 100µm glass with 10 mm x 10 mm x 400µm die (sample #1) at 80 ºC.

Figure 5.6: Shadow moiré data for 25 mm x 25 mm x 100µm glass with 10 mm x 10 mm x 400µm die (sample #1) at 138 ºC.

Figure 5.7: Shadow moiré data for 25 mm x 25 mm x 100µm glass with 10 mm x 10 mm x 400µm die (sample #1) at 202 ºC.

Figure 5.8: Shadow moiré data for 25 mm x 25 mm x 100µm glass with 10 mm x 10 mm x 400µm die (sample #1) at 220 ºC.

Figure 5.9: Shadow moiré data for 25 mm x 25 mm x 100µm glass with 10 mm x 10 mm x 400µm die (sample #1) at 240 ºC.

Figure 5.10: Shadow moiré data for 25 mm x 25 mm x 100µm glass with 10 mm x 10 mm x 400µm die at 260 ºC.

Figure 5.11: Package warpage of 25mm, 100µm glass with 10mm, 400µm die (sample #1) from shadow moiré.

Figure 5.12: Die warpage of 25mm, 100µm glass with 10mm, 400µm die (sample #1) from shadow moiré.

Figure 5.13: Shadow moiré data for 25 mm x 25 mm x 300µm glass with 10 mm x 10 mm x 400µm die (sample #2) at 30 ºC.

Figure 5.14: Shadow moiré data for 25 mm x 25 mm x 300µm glass with 10 mm x 10 mm x 400µm die (sample #2) at 60 ºC.

–  –  –

mm x 400µm die (sample #2) at 80 ºC.

Figure 5.16: Shadow moiré data for 25 mm x 25 mm x 300µm glass with 10 mm x 10 mm x 400µm die (sample #2) at 138 ºC.

Figure 5.17: Shadow moiré data for 25 mm x 25 mm x 300µm glass with 10 mm x 10 mm x 400µm die (sample #2) at 202 ºC.

Figure 5.18: Shadow moiré data for 25 mm x 25 mm x 300µm glass with 10 mm x 10 mm x 400µm die (sample #2) at 220 ºC.

Figure 5.19: Shadow moiré data for 25 mm x 25 mm x 300µm glass with 10 mm x 10 mm x 400µm die (sample #2) at 240 ºC.

Figure 5.20: Shadow moiré data for 25 mm x 25 mm x 300µm glass with 10 mm x 10 mm x 400µm die (sample #2) at 260 ºC.

Figure 5.21: Die warpage of 25mm, 300µm glass with 10mm, 400µm die (sample #2) from shadow moiré.

Figure 5.22: Warpage from shadow moiré for 10 mm x 10 mm x 200 µm silicon die on 25 mm x 25 mm x 150 µm glass interposer (sample #3).

Figure 6.1: (a) Plane-strain model showing all modeled components; (b) zoomed-in image of boxed area from (a).

Figure 6.2: Mesh of plane-strain model from Figure 6.

1(b).

Figure 6.3: 2.

5D model.

Figure 6.4: Example mesh from 2.

5D model.

Figure 6.5: Example of fabrication and assembly process temperatures.

Figure 6.6: “Edge” cross section of package used for warpage modeling

–  –  –

die (sample #1).

Figure 6.8: Predictive model validation for 25mm, 300µm glass with 10mm, 400µm die (sample #2)

Figure 6.9: Predictive model validation for 18.

4mm, 150µm glass with 10mm, 200µm die (sample #3)

Figure 7.1: Predictive model validation (interposer) for 25mm, 100µm glass with 10mm, 400µm die (sample #1).

Figure 7.2: Warpage trend observed in glass interposer packages.

Figure 7.3: Warpage contour plot (at 20x scale) of package with full fillet at 25 ºC.

...... 60 Figure 7.4: Warpage contour plot (at 20x scale) of package with full fillet at 160 ºC..... 61 Figure 7.5: Warpage contour plot (at 20x scale) of package with half fillet at 25 ºC.

..... 61 Figure 7.6: Warpage contour plot (at 20x scale) of package with half fillet at 160 ºC.

... 61 Figure 7.7: Warpage contour plot (at 20x scale) of package with no fillet at 25 ºC.

........ 62 Figure 7.8: Warpage contour plot (at 20x scale) of package with no fillet at 160 ºC.

...... 62 Figure 8.1: “Corner” cross section of package used for reliability modeling.

.................. 64 Figure 8.2: Full temperature model for fabrication, assembly, and thermal cycling........ 66 Figure 8.3: Strain hysteresis loop for (a) xx, (b) yy, and (c) xy components of plane-strain model

Figure 8.4: Solder joint location schematic for solder strain contours.

Figure 8.5: Inelastic strain range contours for glass interposer.

Figure 9.1: Die warpage for a 10 mm, 200 µm-thick die on an 18.

4 mm, 150 µm-thick substrate as function of substrate core material.

–  –  –

Figure 9.3: Inelastic strain range contours for organic substrate.

Figure 9.4: Inelastic strain range contours for silicon interposer

–  –  –

α – coefficient of thermal expansion Δ – Plastic strain range Nf – Fatigue life – Inelastic accumulated strain - Component ij of the strain tensor ̇ – Inelastic strain rate tensor ̂̇ – Rate of accumulated equivalent plastic strain – Deviatoric stress – Equivalent stress ̅ , , , ℎ0, – Material constants for Anand’s model Q – Activation energy for Anand’s model R – Universal gas constant s – Internal state variable s* - Deformation resistance

–  –  –

Tg – Glass transition temperature BGA – Ball Grid Array CTE – Coefficient of Thermal Expansion FE(M) – Finite Element (Method) I/O – Input/Output IC – Integrated Circuit ECTC – Electronic Components and Technology Conference CPMT – Components, Packaging, and Manufacturing Technology

–  –  –

As the microelectronic industry moves toward stacking of dies to achieve greater performance and smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then the silicon interposers are assembled on organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. This work examines the use of diced glass panel as an interposer, as glass provides intermediate coefficient of thermal expansion between silicon and organics, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential interposer material.

Starting with a 150 x 150 mm glass panel with a thickness of 100 µm, this work has built alternating layers of dielectric and copper on both sides of the panel. The panels have gone through typical cleanroom processes such as lithography, electroplating, etc.

Upon fabrication, the panels are diced into individual substrates of 25 x 25 mm and a 10 x 10 mm flip chip with a solder bump pitch of 75 um is then reflow attached to the glass substrate followed by underfill dispensing and curing. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical models have been developed. These models account for viscoplastic behavior of the solder. The models

–  –  –

The warpage from the models has been compared against experimental measurements for glass substrates with flip chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D systems.

–  –  –

As integrated circuits (ICs) have scaled according to Moore’s Law [1], microelectronic packages have also continued to scale over the last several decades with higher interconnect density. As the technologies available have ranged from 2D wirebonded packages through area-array flip-chip and, more recently, 2.5D and 3D, the capabilities of packaging have exponentially increased to provide more I/Os. In doing so, the interconnect pitch has decreased proportionally.



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