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«A Thesis Presented to The Academic Faculty by Xiuping (Yvette) Chen In Partial Fulfillment of the Requirements for the Degree Master of Science in ...»

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EMBEDDED ACTIVE AND PASSIVE METHODS TO REDUCE THE JUNCTION

TEMPERATURE OF POWER AND RF ELECTRONICS

A Thesis

Presented to

The Academic Faculty

by

Xiuping (Yvette) Chen

In Partial Fulfillment

of the Requirements for the Degree

Master of Science in the

G.W. Woodruff School of Mechanical Engineering

MAY 2014

GEORGIA INSTITUTE OF TECHNOLOGY

COPYRIGHT 2014 BY XIUPING (YVETTE) CHEN

EMBEDDED ACTIVE AND PASSIVE METHODS TO REDUCE THE JUNCTION

TEMPERATURE OF POWER AND RF ELECTRONICS

Approved by:

Dr. Samuel Graham, Advisor School of Mechanical Engineering Georgia Institute of Technology Dr. Satish Kumar, Co-advisor School of Mechanical Engineering Georgia Institute of Technology Dr. Yogendra K Joshi School of Mechanical Engineering Georgia Institute of Technology Date Approved: April 4, 2014

ACKNOWLEDGEMENTS

I am grateful to my advisor, Dr. Samuel Graham, for his guidance throughout my research and studies in Georgia Tech. I sincerely thank him for his encouragement, support, inspiration and patience. I wish to thank my co-advisor, Dr. Satish Kumar, for his technical guidance and valuable suggestions throughout my research. I also want to thank Dr. Yogendra Joshi for taking the time to be on my committee. I really appreciate his suggestions.

I would like to thank our research group. I enjoy the time we had spent together and the friendship we had made. I specifically want to thank the members in our GaN group including Jason Jones, Samuel Kim, Georges Pavlidis, Luke Yates, Nazli Donmezer and Sukwon Choi for their valuable suggestions and thoughtful discussions given in our group meetings. I also like to thank my officemates for being caring and humorous, which made my office life more enjoyable.

I want to thank Anne Mallow for her kindness and enthusiasm.

I am extremely grateful to Zhimin Wan, who has spent many hours in teaching me how to use softwares for my simulations in research and help debugging some very difficult problems I have encountered while using the software.

Lastly, I want to thank my family who gives me boundless and unconditional love. I also want to thank my aunt’s family. Without them, I would have not been in the U.S. and certainly would have not owned what I have today.

iii

Table of Contents

ACKNOWLEDGEMENTS

LIST OF TABLES

LIST OF FIGURES

SUMMARY ……………………………………………………………………..xiii CHAPTER 1 INTRODUCTION

1.1 Background for AlGaN/GaN HEMT

1.1.1 Reliability Issue for AlGaN/GaN HEMT

1.2 Background of IGBT

1.3 Research Motivation and Thesis Outline

CHAPTER 2 BACKGROUND

2.1 Introduction

2.2 Thermal Management for AlGaN/GaN HEMT

2.2.1 Standard Cooling method

2.2.2 Advanced heat spreading techniques

2.3 Thermal Management for IGBT

2.3.1 Wire Bonding With Single Sided Cooling

2.3.2 Flip Chip Bonding With Double Sided Cooling

CHAPTER 3 THERMAL-FLUID MODELING OF ALGAN/GAN HEMT.........34

3.1 Introduction

3.2 Chip Definition, Device Geometry and System Layout

3.2.1 Baseline Passively Cooled Devices

3.3 Model Definition

3.3.1 Finite Volume Model of Passive Cooling

3.3.2 Active Cooling Using Integrated Microchannels

3.4 Numerical Analysis

3.4.1 Numerical Assumptions

3.4.2 Mesh Generation

3.4.3 Numerical Model

3.5 Results for Steady Heat Flux at Room Temperature

iv 3.5.1 Comparison between analytical solution and computational solution in passive cooling

3.5.2 Passive Cooling

3.5.3 Microchannel Liquid Cooling

3.6 Simulation Results for Steady Heat Flux at Harsh Environments

3.7 Simulation Results for Unsteady Heat Flux at Room Temperature

3.8 Conclusion

CHAPTER 4 Active Cooling of IGBT Modules

4.1 Introduction

4.2 System Layout and Modeling Definition

4.2.1 Single Sided Cooling

4.2.2 Double Sided Cooling

4.3 Simulation Results

4.3.1 Comparing Different Staggered Pin Fin Spacings

4.3.2 Comparing Double Sided Cooling With Single Sided Cooling

4.4 Conclusion

CHAPTER 5 CONCLUSION AND FUTURE WORK

APPENDIX I

REFERENCES

–  –  –

Table 1.1 Basic properties of semiconductor materials for microwave power transistors [6].

...... 3 Table 1.2 Material properties of substrate and nucleation layers for GaN epitaxy [14] [15] [16].

5 Table 3.1. Thermal conductivity [70] [71] for all substrates and the thermal boundary resistance (tbr) [9] [72] between the substrate and the GaN layer. tbr for both the 1st and 2nd generation GaN-on-diamond devices [9] are shown. * is in plane and ** is out of plane.

Table 3.2 Thickness and thermal conductivity [70] of the materials used in simulations.

........... 40 Table 3.3 Pin fin diameters and spacings for pin fin microchannels. SL represents longitudinal spacing and ST represents transverse spacing.





Table 4.1 Properties of all solid materials used in simulations [71][65].

Table 4.2 Fluid properties used in simulations [54].

Table 4.3 Comparison in heat transfer performance of different staggered pin fin spacings in a microchannels cold plate.

Coolant fluid was 300 K at inlet for all cases.

–  –  –

Figure 1.1 Schematic model showing the formation of a 2DEG at the AlGaN/GaN heterointerface [4].

Figure 1.2 A schematic illustrating advantages of GaN over existing technology [7].

.................. 4 Figure 1.3 Front view of an AlGaN/GaN HEMT device showing all the layers between the heat source and the heat sink.

Figure 1.4 Plot showing exponential relationship between device temperature and failure time [20].

Figure 1.5 I-V characteristics as a function of the applied voltage.

The isothermal simulation (solid line) and measured values (dashed line) are for the AlGaN/GaN on SiC structure [23]...... 9 Figure 1.6 Simplified cross-section of an IGBT.

Figure 1.7 Simplified cross section of (a) a vertical MOSFET and (b) bipolar junction transistor.

Figure 2.1 Stardard cooling structure for AlGaN/GaN HEMT.

Figure 2.2 (a) cross sectional diagram of Titanium thermal ground plane; (b) Etched grooves in titanium substrate with a depth of 250 µm and a width of 350 µm and (c) the titanium is oxidized to produce the Nano-Structrued-Titania structure [35]

Figure 2.3 Operating temperature of single-finger GaN-on-diamond and GaN-on-SiC HEMTs [37].

Figure 2.4 (a) Cross-sectional electron micrograph of a diamond layer deposited at 800 °C and nucleated using a bias voltage; (b) schematic of the grain structure in a micro-scale diamond layer deposited on silicon.

[42] [46]

Figure 2.5 GaN HEMT self-heating simulated for 3.

5 W power dissipation (7 W/mm) [47]...... 21 Figure 2.6 (a) Fabricated copper microchannel heat sink and (b) Zoomed-in view of microchannel [48].

Figure 2.7 Test geometry for the SiC die on a Cu/AlN/Si/SiC microchannel cooler configuration.

Only ¼ of the problem is shown due to symmetry. [49] [50]

–  –  –

Figure 2.9 Image of single crystal SiC heat sink with tree-branch structure.

[51]

Figure 2.10 Cross section of a conventional packaging structure of a semiconductor power device [61].

Figure 2.11 (a) conventional cooling structure and (b) cooling structure with a shorter heat source to coolant path [62]

Figure 2.12 Cross sectional view of a IGBT module with liquid cooling [63].

Figure 2.13 Schematic of the water-spray facility [60].

Figure 2.14 Module with double sided cooling.

Heat sinks were brazed to top and bottom heat sinks [65]

Figure 2.15 Cross section of power semiconductors connected to DBCs using low temperature joining techniques.

Contact pads are not shown in this figure.

Figure 2.16 Cross sections of a packaging structure with heat sinks integrated into DBC substrates in double-sided cooling [68].

Figure 3.1 Close-up of a 6-finger interdigitated HEMT structure showing source (S), gate (G) and drain (D) electrodes.

Figure 3.2 Location of hotspot formation in operational AlGaN/GaN HEMT [5]

Figure 3.3 A die on a CuW Lead Amplifier Package, which was placed on a Cu heat sink.

....... 37 Figure 3.4 Schematic of a cross-section of a packaged AlGaN/GaN HEMT device on a Cu heat sink. Figure not drawn to scale.

Figure 3.5 Side view of a 3-D model for passive cooling.

A constant temperature of 300 K is applied at the bottom of the Cu plate. Heat flux is applied on top of GaN layer as shown in Figure 3.6.

Figure 3.6 A top view of a 3-D thermal model with 30 identical heat flux areas (for 30-finger device) on top of GaN layer.

Dimensions of the heat flux area are labeled.

Figure 3.7 Diamond filled thermal vias inside Si substrate.

Only a quarter of the model is shown.

–  –  –

Figure 3.9 (a) Linear fin microchannel cooler and (b) pin fin microchannel cooler that can be attached to the substrate.

(c) A side view of the linear microchannel cooler with dimensions of the channels and (d) a side view of the pin fin microchannel cooler.

Figure 3.10 Element size sensitivity analysis for passively cooled GaN on Si.

Figure 3.11 Meshing in the system.

Due to the symmetric nature, only half of the whole system is shown here

Figure 3.12 Zoom in view of the meshing of (a) device with integrated microchannels and (b) heat flux areas on top of GaN layer.

Figure 3.13 Meshing of pin fins with water surrounded by.

The dark circles around the pin fins are the inflation layers.

Figure 3.14 Thermal resistance network of passively cooled GaN on SiC.

Figure 3.15 Effect of substrate thickness on peak temperature for Si and SiC substrates with different gate-to-gate spacing and a power density of 4.

1 W/mm. The green dots represent the optimum thickness for each case.

Figure 3.16 Thermal resistances for substrates with different thickness and gate-to-gate (G2G) spacing.

Figure 3.17 Temperature contour for GaN on 50 µm SiC (top) and GaN on 200 µm SiC (bottom) in passive cooling.

Gate-to-gate spacing is 50 µm and power density is 4.1 W/mm................... 60 Figure 3.18 Temperature contour for GaN on 75 µm Si (top) and GaN on 525 µm Si (bottom) in passive cooling. Gate-to-gate spacing is 50 µm and power density is 4.1 W/mm.

Figure 3.19 The temperature profile across the center of each finger (the center of the width) on the top surface of GaN for GaN on 50 µm SiC substrate (blue) and GaN on 200 µm SiC substrate (pink) with 50 µm gate-to-gate spacing and power density of 4.

1 W/mm in passive cooling..... 62 Figure 3.20 The temperature profile along center of each finger (the center of the width) on the top surface of GaN for GaN on 75 µm Si substrate (red) and GaN on 525 µm Si substrate (blue) with 50 µm gate-to-gate spacing and power density of 3 W/mm in passive cooling................... 63

–  –  –

Figure 3.22 The temperature profile along center of each finger on the top surface of GaN for GaN on 75 µm Si substrate with and without diamond thermal vias.

Both cases have 50 µm gateto-gate spacing and power density of 4.1 W/mm.

Figure 3.23 Power density vs.

volumetric flow rate for different gate-to-gate spacing “G2G” and substrate materials. The power density corresponds to the maximum power density in the device to have a junction temperature no higher than 200 °C. Optimum thicknesses were used for the substrates.

Figure 3.24 Hydrodynamic entry length and average heat transfer coefficient in linear microchannal as a function of water flow rate.

Figure 3.25 (a) Maximum power dissipation (for a maximum temperature of 200 °C) as a function of flow rate and (b) bulk fluid temperature rise as a function of flow rate with a corresponding power dissipation shown in (a) for GaN on Si and GaN on SiC with linear microchannels and 50 µm gate to gate spacing.

Figure 3.26 Thermal resistance for GaN on Si and GaN on SiC substrates with linear fin microchannel and different gate-to-gate spacing.

Figure 3.27 (a) is the top view of the temperature distribution on the GaN layer and (b) is the zoom-in view of the middle part of the inner-most finger (circled area in (a)).

Figure 3.28 Percentage of heat dissipated by water vs.

flow rate with uses of SiC and Si linear microchannels with 50 µm gate-to-gate spacing.

Figure 3.29 Comparison of power density between different microchannel designs under the 200 °C maximum temperature and 200 kPa pressure drop conditions.



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