«A Dissertation Presented to The Academic Faculty by Zhimin Wan In Partial Fulfillment of the Requirements for the Degree Doctoral of Philosophy in ...»
TRANSPORT CHARACTERISTICS OF PIN FIN ENHANCED
MICROGAPS UNDER SINGLE AND TWO PHASE COOLING
The Academic Faculty
In Partial Fulfillment
of the Requirements for the Degree
Doctoral of Philosophy in the
School of Mechanical Engineering
Georgia Institute of Technology
COPYRIGHT © 2016 BY ZHIMIN WAN
TRANSPORT CHARACTERISTICS OF PIN FIN ENHANCED
MICROGAPS UNDER SINGLE AND TWO PHASE COOLING
Dr. Yogendra K. Joshi, Advisor Dr. Saibal Mukhopadhyay School of Mechanical Engineering School of Electrical and Computer Georgia Institute of Technology Engineering Georgia Institute of Technology Dr. Andrei Fedorov Dr. Sudhakar Yalamanchili School of Mechanical Engineering School of Electrical and Computer Georgia Institute of Technology Engineering Georgia Institute of Technology Dr. Satish Kumar School of Mechanical Engineering Georgia Institute of Technology Date Approved: [April 25, 2016] To my grandmother To my parents To my brothers
ACKNOWLEDGEMENTSI would like to deeply thank all the people who have helped me during my doctoral study at Georgia Tech.
First and foremost, I would like to thank my advisor, Dr. Yogendra Joshi, for his continuous guidance, support, encouragement. His passion and vision always inspire me to think more and differently about my research. I really enjoyed our discussions over the years and his valuable suggestions helped me a lot when I encountered difficulties in my research. I cannot thank him enough for his outstanding mentorship and kindness.
I am very grateful for my committee members, Dr. Andrei Fedorov, Dr. Satish Kumar, Dr. Saibal Mukhopadhyay, and Dr. Sudhakar Yalamanchili for their time and valuable feedback throughout my PhD proposal and defense process. Part of this work was performed in collaboration with Dr. Saibal Mukhopadhyay and Dr. Sudhakar Yalamanchili. I learned a lot about chip architectures and gained insight into the challenges of cooling-architecture co-design of microprocessor. I would like to acknowledge the financial support from Cisco Systems, Inc., Sandia National Laboratories, and National Science Fundation.
I extend my thanks to Dr. Muhannad Bakir, Dr. Yue Zhang, Dr. Li Zhen, and William Song from School of Electrical and Computer Engineering, for their valuable time, advice. I would specially like to thank Dr. Wen Yueh and He Xiao for their help and discussion on the modelling and experimental study of electrical performance of microprocessors.
Microelectronics and Emerging Technologies Thermal Laboratory (METTL) for their assistance, friendship. Especially, I want to thank Xuefei Han for her help on numerical modeling, Dr. Craig Green for his help on experiment test, Dennis Tung for his help on microfabrication, Dr. Aravind Sathyanarayana for his valuable discussion on the study of mixture.
I am very grateful to all the staff members at the Microelectronics Research Center (MiRC) for their help and guidance with the microfabrication tools and processes in the cleanroom. Especially, I would like to thank Tran-Vinh Nguyen, Charlie Suh, Hang Chen, Chris Yang, Thomas Johnson-Averett, and Mikkel A. Thomas. Without their help, I cannot finish my fabrication of test samples.
I am also grateful to all the staff members at the School of Mechanical Engineering.
I would like to thank Ms. Glenda Johnson for her help on my graduate study, Ms. Regina Neequaye for help in timely ordering all the experiment stuff, Mr. Kyle French for his help on the printed circuit board (PCB) fabrication, Steven Sheffield for his help on the machining of the test package.
Last but not least, I express my deepest gratitude to my grandparents, parents and brothers for their unconditional love and support. Without their support and love, I would not have been in this position today.
Table 4.4: Coefficients for friction factor correlation for circular pin fin arrays.
70 Table 4.5: Coefficients for Colburn j factor correlation for circular pin fin arrays. 73 Table 4.6: Coefficients for friction factor correlation for square pin fin arrays.
74 Table 4.7: Coefficients for Colburn j factor correlation for square pin fin arrays 74
Table 5.4: Optimization results for non-uniform heat dissipation without hotspot.
95 Table 5.5: Optimization results for non-uniform heat dissipation with hotspot.
Figure 2.1: Schematic of micro pin fin heat sink with embedded signal vias.
28 Figure 3.1: Mask design for the microgaps with staggered pin fin arrays on a 4” wafer.33 Figure 3.2: Mask design and schematic of the 4 heaters and 12 temperature sensors. 34
Figure 3.7: Design of PCB illustrating the pads for soldering and wirebonding.
42 Figure 3.8: Assembly of device, package, and PCB (a) Device attached on PCB by double side tape, (b) PCB flipped and locked with package by nuts.
Figure 4.2: Front view of a section of the numerical mesh with a body size 6 μm.
54 Figure 4.3: Schematic illustrating the location of temperature sensors.
Figure 4.10: Friction factor versus ratio of pin fin height to pin diameter.
68 Figure 4.11: Friction factor versus ratio of transversal spacing to pin diameter.
68 Figure 4.12: Friction factor versus ratio of longitudinal spacing to pin fin diameter.
Figure 4.20: Heat transfer coefficients comparison between square and circular micro pin fin arrays under same pumping power with 1cm × 1cm chip.
Figure 5.18: Schematic and experimental assembly of CMOS chip, microgap, PCB.
104 Figure 5.19: Natural convection air cooling. (a) Chip average temperature changes with heat flux, (b) Leakage current changes with chip average temperature. 106 Figure 5.20: Comparison of natural convection air cooling, forced convection air cooling, and microfluidic cooling: (a) Chip average temperature changes with heat flux, (b) Leakage current changes with chip average temperature. 107
Microfluidic convection cooling is a promising technique for future high power microprocessors, radio-frequency (RF) transceivers, solid-state lasers, and light emitting diodes (LED). Three-dimensional (3D) stacking of chips is a configuration that allows many performance benefits. A microgap with circulating fluid is a promising cooling arrangement that can be incorporated within a 3D chip stack. Although studies have examined the thermal characteristics of microgaps under both single-phase and two-phase convection, the characteristics and benefits of microgaps with surface enhancement features have not been fully explored. In this work, firstly, the single phase thermal/fluid characteristics of microgaps with staggered pin fin arrays are studied. The effects of the pin fin dimensions including diameter, transversal and longitudinal spacing, and height are investigated computationally and experimentally over a range of Reynolds number (Re) 22-357. Micropin fin arrays investigated have pin diameter of 100 μm, pitch/ diameter ratios of 1.5 ~ 2.25, and height/ diameter ratios of 1.5 ~ 2.25. Correlations of friction factor (f) and Colburn j factor for these dense arrays of micro pins have been developed.
Subsequently, microfluidic cooling with staggered pin fin arrays is employed in functional 3D integrated circuit (ICs). Thermal and electrical performance of a CMOS chip in terms of temperature and leakage power under realistic operating conditions are studied. Both experimental and modeling results show that microfluidic cooling could significantly decrease the chip temperature and leakage power, thus increasing the chip performance.
Lastly, two-phase cooling is studied with dielectric fluid HFE-7200 as a baseline with mass flux from 354.5 kg/m2-s to 576.3 kg/m2-s. Critical heat flux (CHF) increases with increasing mass flux but decreases with decreasing gap height. Nonuniform heating will
the thermal performance. The effects of fluid mixture (HFE-7200/Methanol) on thermal performance are studied with mass fraction of Methanol from 8.5% to 35.8%. A very small amount of addition of Methanol (8.5% mass fraction) can significantly increase the thermal performance due to the sharp decrease of saturation temperature, increase of effective thermal conductivity and latent heat. However, the Marangoni effect caused by the concentration gradient deteriorates the CHF.
The pursuit of multi-functionality and low cost for either military or consumer electronics, such as radio-frequency (RF) transceivers, solid-state lasers, light emitting diodes (LED), and future high power microprocessor, continues pushing up the power consumption and power density of these devices. For example, Gallium-nitride (GaN) high electron-mobility transistors (HEMT) have power densities many times higher than other power transistor technologies. The output power density of a N-polar GaN HEMTs with a drawn gate length of 0.7 μm and a gate drain spacing of 0.8 μm can be 12.1 W/mm , resulting in a heat flux of 1.5×106W/cm2. A pulse of sub-picosecond duration and petawatt (PW) power was first reached at the Lawrence Livermore National Laboratory in 1996, and the Jan USP laser developed there has a peak power intensity of 2×10 20W/cm2 .
Another common example of a high heat flux device is the microprocessor for which the “Moore’s law”  has been the driving force for development . The feature size has become smaller and transistor count increased with each technology node to improve IC functionality and performance, while decreasing costs . From 1971 to 2012, the feature size decreased from 10 μm to 22 nm, the transistors count increased from 2,300 to 1.4 billion, and the clock speed increased from 108 kHz to 2.9 GHz. At the same time, each transistor used about 5,000 times less energy and the price per transistor has dropped by a factor of about 50,000 . The latest International Technology Roadmap for Semiconductors (ITRS)  shows that the transistor density on a logic chip was about
the transistor count is increasing, the packaging size continues to shrink due to the customer expectations for small form factor products and technology development . Packaging technologies have evolved significantly from the early stage dual in-line package (DIP), and ball grid arrays (BGA), to more recent system-on-chip (SOC), system-in-package (SIP), package-on-package (PoP), and three-dimensional integrated circuits (3D ICs).
Although Moore’s law has proved its success in predicting the technology trends until recently, such scaling has now slowed down . The 2012 update to the ITRS  had growth slowing and predicted that the transistor density will double only every three years after 2013. Several factors are behind this trend. First, the size of transistor cannot be miniaturized indefinitely since it will eventually reach the fundamental physical barrier . If the thickness of gate oxide layer is less than four layers of silicon atoms, the current will penetrate through the gate oxide, which leads to the failure of the transistor. Secondly, the scaling of the transistor and interconnect are not developed in the same step. While the transistor becomes faster and smaller, the global interconnect does not. Indeed the interconnects have become a major bottleneck for high performance computing systems, instead of transistors . Continuing to extend Moore’s law by increasing the transistor density in planar direction results in longer interconnects and increase in latency. It is reported that the interconnects latency will exceed that of transistor for interconnect length greater than 30 μm . Also, the longer interconnects consume more power due to Joule heating. All of the above factors will cause degradation of the performance and reduce the expected benefits from scaling.
stacked directly for 3D ICs. 3D ICs could overcome the problems associated with 2D IC [9-11], and thus promise continuation of Moore’s law in the out-of-plane direction. The vertical integration of chips could reduce the wire interconnection length by as much as 50% . The global RC delay could thus be reduced and the wire-limited clock frequency increased by 3.9 X . Also, the wire-limited power consumption in the interconnection could also be reduced . Wide bandwidth buses between functional blocks in different chips could be achieved . Lastly, 3D integration allows realization of various heterogeneous technologies including memory, logic, radio frequency (RF), and optoelectronics within a single block, increasing package functionality and reducing size.
1.1.1 Motivation for Microfluidic Cooling Although the energy per transistor is decreasing because of the decreasing supply voltage, the total chip power is increasing due to the increase in transistor count. The power density is also increasing due to the decreasing packaging size. The power distribution on a die is usually non-uniform with some high power regions, hotspots with larger power density . The power on a chip is continually increasing, and the maximum heat flux on an automotive electronics chip was about 240 W/cm2 in 2013. It is projected that the hotspot power density could be greater than 300 W/cm2 in 2015 . If not effectively removed, it would result in high chip temperatures, which will increase the leakage power exponentially, degrade the computational performance, and possibly even accelerate failure of the device .