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«A Dissertation Presented to The Academic Faculty by Bing Dang In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the ...»

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Integrated Input/Output Interconnection and

Packaging for GSI

A Dissertation

Presented to

The Academic Faculty

by

Bing Dang

In Partial Fulfillment

of the Requirements for the Degree

Doctor of Philosophy in the

School of Electrical and Computer Engineering

Georgia Institute of Technology

December 2006

Copyright 2006 by Bing Dang

Integrated Input/Output Interconnection and

Packaging for GSI

Approved by:

Dr. Gary S. May

Dr. James. D. Meindl

School of Electrical and Computer School of Electrical and Computer Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology Dr. Yogendra K. Joshi Dr. Sunk-kyu Lim School of Mechanical Engineering School of Electrical and Computer Georgia Institute of Technology Engineering Georgia Institute of Technology Date Approved: July 11, 2006 Dr. A. Bruno Frazier School of Electrical and Computer Engineering Georgia Institute of Technology Acknowledgement I would like to thank Prof. James D. Meindl for his guidance, inspiration, and support throughout my Ph.D. study. I am also very grateful to Prof. Sunk-Kyu Lim, Prof. Brouno Frazier, and for their time to review my dissertation. Thanks are also extended to Prof. Yogendra Joshi, Prof. Paul Kohl, Dr. Xiaojin Wei, and Dr. Paul Joseph for their great help. I would also like to express my gratitude to Jennifer Tatham Root for her continuous help and support during my dissertation years. My dissertation benefited so much from discussion and collaboration with my fellow GSI group members. Particularly, I would like to thank Dr. Muhannad Bakir for his help and insights. I would like to thank Deepak Sekar for a lot of discussion and help. In addition, thanks are extended to Dr. Kevin Martin, Joel Pikarsky, Gary Spinner, and cleanroom staff.

I would like to thank my parents, my wife, and my sisters, for their understanding and endless support. I also want to thank my wonderful daughter, Ashley Y. Dang.

iii Contents Acknowledgement

List of Tables

List of Figures

Summary

Chapter 1. Introduction and Background

1.1. Area Array Chip-to-Package Interconnection

1.1.1. C4 Flip-chip Interconnection

1.1.2. Compliant Wafer-Level Chip I/O Interconnection

1.2. Advanced Chip Cooling

1.2.1. Limitations of Air-cooled Heat Sinks

1.2.2. Liquid Cooling and Microfluidic Heat Sinks

1.2.3. Opportunity of the Integrated Thermal-fluidic Packaging

1.3. Integrated Electrical, Optical and Thermal-fluidic I/O Interconnections

1.4. Summary of Research Goals

1.5. Organization of the Dissertation

Chapter 2. Implementation of the MEMS-based Sea-of-Leads Interconnects.

............... 22 2.1. Introduction

2.2. Integration of the MEMS-based SoL with an IBM Bumping Process

2.2.1. Lead Releasing by Undercut of the Adhesion Layer

2.2.2. Integration with Wafer Bumping Processes through Masked Evaporation.......... 26

–  –  –

Electroplating Wafer Bumping

2.3.1. Lead Releasing by a Sacrificial Layer

2.3.2. Integration with Wafer Bumping Process by Electroplating

2.4. Assembly of SoL MEMS Interconnects by Flip-Chip Bonding

2.5. Thermal-mechanical Reliability Study

2.6. Summary

Chapter 3. Structural Characterization for SoL MEMS Interconnects

3.1. Introduction

3.2. Micromechanical Finite Element Modeling

3.2.1. Mechanical Benefits of the SoL MEMS Interconnects

3.2.2. Package Weight Supportability Issues

3.3. Structural Effects

3.3.1. Structural Effect on Mechanical Compliance

3.3.2. Effect of Lead Aspect Ratio (t/w) on Mechanical Compliance

3.3.3. Structural Effect on Electrical Parasitics

3.4. General Design Guidelines

3.5. Summary

Chapter 4. Fabrication of an On-Chip Microchannel Heat Sink and Assembly with Thermal-fluidic I/O Interconnects

4.1. Introduction

4.2. CMOS Compatible Fabrication of On-chip Microfluidic Channels

–  –  –

4.2.2. Monolithic Fabrication of Microfluidic Channels using a Sacrificial Polymer.... 74 4.2.3. Testing of the Polymer-capped Microchannels

4.3. Fabrication of Integrated Thermal-fluidic I/O Interconnects

4.3.1. Thermal-fluidic Through-vias

4.3.2. Trench Filling Issues with the Presence of the Through-vias

4.3.3. Integrated Electrical/Thermal-fluidic I/O Interconnects

4.4. Wafer-level Integration of the Microchannel Heat Sink

4.5. Chip-to-board Thermal-fluidic I/O Interconnection

4.5.1. Assembly of “Microfluidic Flip Chips”

4.5.2. Integrated Thermal-fluidic I/O Configurations

4.5.3. Fabrication of Channel Networks on Low-cost Organic Board Substrates........ 112

4.6. Summary

Chapter 5. Thermal-fluidic Characterization of an Integrated Microchannel Heat Sink

–  –  –

5.1. Introduction

5.2. Thermal Resistance Analysis for an On-chip Microchannel Heat Sink

5.3. Benefits of Microchannel Liquid Cooling

5.3.1. Benefits of Integrated Thermal-fluidic Heat Sink for Cooling of “Hot Spots”.. 120 5.3.2. Benefits of Low-temperature Operation for GSI Chips





5.4. Hydraulic Analysis and Challenges for the Integrated Microchannel Heat Sink....... 123

5.5. Thermal-Fluidic Demonstration and Measurement

–  –  –

5.5.2. Thermal-Fluidic Measurements

5.6. Summary

Chapter 6. Compatible Electrical, Optical, and Thermal-fluidic I/O Interconnects Based on Polymer Pillars

6.1. Introduction

6.2. Fabrication of Dual-mode Polymer Pillar-based I/O Interconnects

6.3. Electrical Resistance and Current Carrying Capability of Dual-mode Polymer Pillar

–  –  –

6.4. Assembly of Dual-mode Electrical/Optical Polymer Pillars

6.5. Demonstration of Electrical/Optical Interconnection using Waveguide Volume Grating Coupler

6.6. Demonstration of Optical Interconnection through Slanted Si Mirror

6.7. Compatible Electrical, Optical and Thermal-fluidic I/O Interconnects

6.7.1. Polymer Pillars as the Building Block

6.7.2. Fabrication of Integrated Packaging Substrate with Electrical, Optical, and Thermal-fluidic Interconnects

6.8. Summary

Chapter 7. Conclusion and Future Work

7.1. Conclusion

7.1.1. MEMS-based SoL Compliant I/O Interconnects for GSI

7.1.2. Integrated Thermal-fluidic I/O Interconnection and Packaging

–  –  –

7.2. Future Work

7.2.1. Bumping of SoL Interconnects with Lead-free Solder Alloys

7.2.2. Design Optimization of SoL Interconnects

7.2.3. Metal -capped Monolithic Microchannels

7.2.4. Optimization of Geometries and Dimensions for the On-chip Microchannel Heat

–  –  –

7.2.5. Solder-based Hermetic Sealing for Thermal-fluidic I/Os

7.2.6. Design of Integrated Thermal-fluidic Systems

7.2.7. Integrated Thermal-fluidic Networks for 3-D Cooling

7.2.8. Enhanced Microfluidic cooling of “hot-spots”

7.2.9. Reliability Study for Thermal-fluidic Interconnection

7.2.10. Simultaneous Assembly of Electrical/Optical/Thermal-fluidic I/O Interconnects 190 7.3. Conclusion of the Dissertation

References

Vita

–  –  –

Table 1.1: Summary of various compliant chip I/O interconnect technologies [1.

22-1.33].......... 8 Table 1.2: Summary of the thermal resistance of the components in a typical flip-chip package for microprocessors [1.

11, 1.27, 1.36, 1.39-1.42]

Table 2.1: Summary of the results of Cu undercut etching experiments with Al etchant (type A) at various temperatures for different etching time

Table 2.2: Summary of the sacrificial materials for lead releasing

Table 2.3: Stand-off height and calculated resistance of a completed SoL interconnect.

............ 39 Table 3.1: Material properties for the FEM [3.

5, 3.9].

Table 3.2: Summary of vertical deformation for several package weight cases [3.

9].................. 58 Table 4.1 Processing conditions for trench filling with high-viscosity polymer for various channel dimensions

Table 4.2 Heat treatment temperature profiles of Unity 200P and Unity 200NP in a nitrogenpurged oven

Table 4.3.

Physical properties of various dielectric polymers used in wafer-level packaging applications [4.13, 4.16, 4.17]

Table 5.1 Summary of achievable thermal resistance of single-phase on-chip microchannel heat sinks reported in literature [5.

1, 5.3, 5.5 – 5.7]

Table 6.1: ITRS projections for 18nm technology node in 2018 [6.

2]

Table 6.2: Processing conditions for the high aspect-ratio polymer structures using Avatrel 2195 and SU-8.

–  –  –

Figure 1.1: Schematic of chip-package I/O interfacing for a GSI chip.

Figure 1.2: Schematic of a flip-chip on an organic PWB substrate with underfill

Figure 1.3: ITRS projection of area array bump pitch vs.

technology node [1.3].

Figure 1.4: Illustration of delamination of chip pads under thermal-mechanical stress in the low-k interconnect systems [1.

5].

Figure 1.5: ITRS projection of (a) power dissipation (b) calculated thermal resistance (junction to ambient) of a single chip package for high performance and cost performance applications.

....... 9 Figure 1.6: Schematic of a conventional forced-air heat sink for a typical flip-chip package.

.... 11 Figure 1.7: Plot of achievable thermal resistance as a function of heat transfer coefficient for the forced air, free liquid cooling, forced liquid cooling and phase-change cooling [1.

36]. (The blue solid line represents the thermal-resistance of a typical forced air-cooled heat sink and the blue dotted line represents the ITRS projection for a high-performance chip in 2018 [1.3]).............. 14 Figure 1.8: Schematic of typical microchannel heat sinks in literature (a) the microchannel heat sink is integrated as part of a Si chip [1.

9, 1.48] (b) the microchannel heat sink is fabricated separately and attached onto the back side of a chip with a TIM [1.46, 1.49].

Figure 1.9: The conceived schematic for a multi chip system with the chip-level liquid cooled heat sink and individual tubing at the back side of each chip

Figure 1.10: Examples of board-level fluidic channels for heat dissipation: (a) thermal-fluidic channels in LTCC board [1.

56] and (b) thermal-fluidic channels in FR-4 organic board [1.58]. 17 Figure 1.11: Schematic illustrating how the polymer pillars compensate for the CTE mismatch between the board and the die and maintain optical alignment during thermal cycling [1.

71].... 19 Figure 2.1: Optical micrograph of the electroplated metal leads to be released by controlled undercut etching: an etch window is defined by photoresist to control the undercut progress.

... 23 Figure 2.2: Optical micrographs of the electroplated metal leads in various conditions (a) leads can not be peeled without enough undercut etching, (b) leads are not released because of nonuniform undercut etching, (c) successful releasing resulted from a good undercut etching, (d) detaching due to the over-etching.

x Figure 2.3: Schematic of the process integration with evaporation wafer bumping processes after lead releasing: (a) Begins with the released leads, (b) Deposit BLM through evaporation, (c) Deposit and pattern the Ti/SiO2 ring, (d) Electroless plating of Ni/Au, (e) Deposit C4 bumps through evaporation, (f) Solder reflow

Figure 2.4: Illustration of the mask removal issue for the C4 bump evaporation processes.

....... 27 Figure 2.5: Optical micrograph of the damaged leads caused by the Mo mask

Figure 2.6: Illustration of the lead detaching problem with undercut wet etching approaches.

(wet etching undercuts the anchoring portion of a lead)

Figure 2.7: Illustration of lead releasing with a sacrificial layer (since the adhesion layer is not affect during releasing step, lead detaching is not a problem)

Figure 2.8: SEM photograph of MEMS leads after the release process: (a) metal leads after removal of sacrificial layer and (b) an area after destructive peeling test with an adhesive tape, which clearly confirms that leads are flexible but well-anchored.

Figure 2.9: Optical photograph of the on-chip interconnects, which include Cu pads covered by SiO2 passivation.

The vias have a diameter of 50µm and a pitch of 325µm.

Figure 2.10: Illustration of the integration of SoL MEMS interconnects onto a BEOL wafer and bumping of the SoL interconnects through electroplating: (a) BEOL process completes, (b) deposition of a sacrificial layer, (c) deposition of a seed layer, (d) Patterning and plating of leads

Figure 2.11: SEM photographs of the completed SoL MEMS interconnects (hgap~2µm;

tlead~7µm; tUBM~3.5µm; hbump~25µm; overall height~42.5µm)

Figure 2.12: Illustration of the importance of a solder dam on a SoL MEMS interconnect (without such a solder dam, wicking can easily occur during solder reflow process).

................. 38 Figure 2.13: SEM photograph of the soldered Ni UBM revealed by hot air

Figure 2.14: Illustration of a handling issue during the dicing process with high pressure DI water: the SoL MEMS interconnects may be lifted up by localized high-pressure impact.



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