«A Dissertation Presented to The Academic Faculty By Ahmet Ceyhan In Partial Fulﬁllment of the Requirements for the Degree Doctor of Philosophy in ...»
INTERCONNECTS FOR FUTURE TECHNOLOGY
GENERATIONS—CONVENTIONAL CMOS WITH
COPPER/LOW–κ AND BEYOND
The Academic Faculty
In Partial Fulﬁllment
of the Requirements for the Degree
Doctor of Philosophy
Electrical and Computer Engineering
School of Electrical and Computer Engineering
Georgia Institute of Technology
December 2014 Copyright © 2014 by Ahmet Ceyhan
INTERCONNECTS FOR FUTURE TECHNOLOGY
GENERATIONS—CONVENTIONAL CMOS WITH
COPPER/LOW–κ AND BEYOND
Dr. Azad Naeemi, Advisor Dr. Saibal Mukhopadhyay Associate Professor, School of ECE Associate Professor, School of ECE Georgia Institute of Technology Georgia Institute of Technology Dr. Jeffrey A. Davis Dr. Yogendra Joshi Associate Professor, School of ECE Professor, School of ME Georgia Institute of Technology Georgia Institute of Technology Dr. Muhannad Bakir Associate Professor, School of ECE Georgia Institute of Technology Date Approved: December 2014 To my parents, Belgin and Cumhur Ceyhan who taught me patience and persistence
ACKNOWLEDGMENTSI would like to express my deepest gratitude to my thesis advisor, Professor Azad Naeemi, for his unwavering guidance, constructive criticism and insightful sug- gestions throughout my studies at Georgia Tech. His invaluable insight in the design and potential problems of future interconnect technologies has directly shaped the work in this thesis. It has been a real privilege to work with him and I will cherish all the lessons that I have learned from him, both during my career and in my personal life.
I feel very lucky that I had the great pleasure of working with the wonderful people of the Nanoelectronics Research Lab. I would like to thank Shaloo for al- ways being a positive inﬂuence on all of us and bringing down the walls between our cubicles by organizing events to get us together outside of the academic envi- ronment. I really enjoyed discussing potential research topics with Vachan and I am grateful to him for taking the time to brainstorm with me because many of our discussions have led to practical ideas to further my research and some have even become publications. I also wish to thank Nick for always putting a smile on every- one’s faces, being a trustworthy friend to me and always happily extending his full assistance on many occasions, sometimes even before I asked. I must also thank Anant, Omar, Chenyun, Sou-Chi, Phillip, Sourav, Divya, Rouhollah and Ramy for the invaluable feedback they have given me during many of my presentations.
I am thankful to Professor Jeff Davis and Professor Saibal Mukhopadhyay for being on my proposal committee, reading my thesis and sharing their useful ideas about the direction of my research. I would also like to extend my sincere thanks to Professor Muhannad Bakir and Professor Yogendra Joshi for agreeing to be on my dissertation committee and for their insightful discussions and questions about the results of my research.
led to my decision to pursue a doctorate degree. I’m also grateful to my friends Kemal, Erdem, Selcuk, Giray and Baris, for being my brothers away from my family. You have made some of the really hard times during the last ﬁve years seem more tolerable with your support and encouragement.
I am extremely grateful to my parents for all their sacriﬁces, all the long hours of phone conversations in the middle of the night and never making me feel alone as I struggled to achieve my goals. I am deeply indebted to them for their patience during this time and I hope that I have made them proud with this dissertation.
The completion of this dissertation would not have been possible without one person beside me. Lena, the most important support, both direct and indirect, that I have received has been from you. You have stayed up with me before deadlines, taken care of me during the worst sickness of my life, and embraced my goals as your own. I cannot begin to express my thanks to you for all the positivity you brought into my life and the energy you have given me in times of despair. Your steadfast support and profound belief in me has been and will continue to be my greatest strength at every step as I achieve my goals one by one.
Table 1 Interconnect technology parameter projections related to the latency of interconnects extracted from the 2011 update of ITRS .
Calculated metrics are indicated with the * sign........... 7
Table 4 Various published experimental Cu size effect parameters...... 21 Table 5 Multilevel interconnect network design results in 2012........ 24
Table 7 Multilevel interconnect network design results in 2020 showing interconnect pitch and range of interconnect lengths routed at each metal level normalized to gate socket lengths (99 nm)........ 30 Table 8 Multilevel interconnect network design results in 2020 showing interconnect pitch and range of interconnect lengths routed at each metal level normalized to gate socket lengths (99 nm)........ 31
Effective Cu resistivity values normalized to 1.8µΩ · cm. InterconTable 10 nect scenarios are listed in order of reducing severity........ 40 Table 11 Cell delays at various interconnect scenarios calculated at a medium input slew/output load case. Input slew=18.75ps (14.06ps for DFF), output load=0.64/0.88/1.76/3.2 f F at 45/22/11/7-nm technology nodes, respectively............................. 42
Table 19 Design results for the AES circuit using the 7–nm technology node FEOL with 7–and 11–nm BEOL options with 5 metal levels..... 59 Table 20 Design results for the AES circuit using the 7–nm technology node FEOL with 7–and 11–nm BEOL options with extra metal levels... 59 Table 21 Driver and interconnect parameters for high–performance circuits at the 7.5–nm technology node...................... 74
Figure 2 Microprocessor trend data: The changes in the transistor count, single–thread performance, frequency, power, and number of cores are plotted for the past 35 years. Adapted from .......... 9
Figure 4 Number of metal levels is plotted versus the technology year considering a range of size effect parameters. Mitigating size effects can reduce the number of metal levels signiﬁcantly.......... 23 Figure 5 Interconnect delay distribution calculated for the worst case of size effects (straight line) and single-crystal Cu assumption (dashed line) in 2012. Each discontinuity corresponds to switching to a new metal level. For both cases, there are as many individual lines as the number of metal levels................... 25
(a) resistance p.u.l., r, (b) capacitance p.u.l., c, (c) intrinsic interFigure 7 connect rc delay p.u.l. squared, and (d) total delay assuming short (3 µm, ∼10 gate pitches, solid line) and longer (45 µm, ∼150 gate pitches, dashed line) interconnects, respectively, are plotted versus aspect ratio at the 7–nm technology node. Size effect parameters are taken as psize = 0 and Rsize = 0.43............... 28 rc delay p.u.l squared for various width values considering an Figure 8 interconnect pitch of 24 nm in 2020 and size effect parameters psize = 0, Rsize = 0.43. The inset ﬁgure shows the percentage variation in rc delay versus the variation in width as a percentage of the nominal width value for various interconnect pitches..... 30 Figure 9 Interconnect and total power dissipation in the logic cores calculated from the optimal MIN design at various technology nodes considering a range of size effect parameters.............. 33
Figure 11 Placement and routing results for AES, LDPC and FFT considering a pessimistic scenario for interconnect size effects........ 44 Figure 12 The simulated structures for well-aligned and misaligned via structures at the 7–nm technology node.................... 53 Figure 13 Placement density for the AES circuit assuming 7nm FEOL + 11nm BEOL structure and the routing congestions at M2.......... 58 Figure 14 (a) Reference Cu interconnect conﬁguration considered in this paper. W, T, S and H stand for the interconnect width and interconnect thickness, spacing between interconnects and the interlayer dielectric thickness, respectively, (b) Few SWNTs interconnect conﬁguration. P stands for the interconnect pitch and D stands for the tube diameter. Tubes are assumed as randomly distributed in consecutive regions of half a pitch separated by forbidden regions of the same width.................... 66 Figure 15 Top view of the SWNT interconnect conﬁguration. Tubes are randomly placed. In this work, considering the advances in manufacturing long, dense and well–aligned SWNTs, we assume that the lengths of the tubes are homogeneous, but they may be broken at a random location along the length and the distance between consecutive tubes may vary........................ 66 Figure 16 Comparison of the resistance p.u.l. associated with Cu interconnects and SWNT interconnects considering various number and diameter of tubes in a single layer. The resistance p.u.l. for a SWNT bundle of 1 nm diameter tubes is also shown as reference, where it is optimistically assumed that the density of metallic tubes in the cross–section of the bundle is 1/3nm2 , higher than the Van der Waals limit of only 1/4.5nm2............. 68 Figure 17 Comparison of the capacitance p.u.l. associated with Cu interconnects and SWNT interconnects considering various number and diameter of tubes in a single layer. The capacitance p.u.l. for a SWNT bundle is the same as the Cu interconnects ........ 68 Figure 18 Comparison of the RC product p.u.l. squared associated with Cu interconnects, bundles of SWNT interconnects and SWNT interconnects considering various number and diameter of tubes in a single layer. The bundles are the same size as Cu interconnects and the density of metallic tubes in the cross–section of the bundle is assumed to be 1/3nm2 .................... 70
Figure 20 Comparison of the RC product p.u.l. squared associated with Cu interconnects and SWNT interconnects considering various number of tubes in a single layer and the effect of possibly broken tubes. Only the worst case is plotted when the impact of broken tubes are considered........................... 71
Figure 22 The schematic for the complete circuit simulated in HSPICE shown for a three-tube SWNT interconnect design............... 73 Figure 23 Speedup offered by single or few SWNT interconnect designs with various number of tubes and bundles of SWNTs as a function of interconnect length assuming that drivers and receivers are 5× the minimum size. Kinetic inductance is assumed to be equal to its theoretical value, which is 8nH/µm per conduction channel... 75 Figure 24 EDP offered by single or a few SWNT interconnect designs with various number of tubes and bundles of SWNTs as a function of interconnect length assuming that drivers and receivers are 5× the minimum size. Kinetic inductance is assumed to be equal to its theoretical value, which is 8nH/µm per conduction channel... 76
Figure 29 The RC delay of a 10–gate–pitch–long interconnect is plotted versus the technology generation for various experimentally reported size effect parameters. For reference, the bulk Cu resistivity scenario and intrinsic delay of CMOS switches based on ITRS projections are also plotted. For the 16–nm technology node, intrinsic delays of CMOS and CNFET switches are shown based on ASU predictive models and Stanford University CNFET model, respectively [98, 99, 103]............................. 83 Figure 30 The EDP comparison for the same items in Figure 29......... 83
Figure 33 Optimal number of repeaters required for CMOS circuits and CNFET circuits under various conditions.................. 88
Figure 36 Total interconnect power dissipation of the MIN for various core sizes assuming different technologies.................. 91 Figure 37 Total power dissipation of the MIN including dynamic and leakage power of logic gates and repeaters................. 92 Figure 38 Number of required metal levels for various clock frequencies assuming different technologies...................... 93 Figure 39 Total interconnect power dissipation of the MIN at various clock frequencies assuming different technologies.............. 94 Figure 40 Total power dissipation including dynamic and leakage power of logic gates and repeaters at various clock frequencies......... 94
Figure 42 Device architectures for FinFET (top left), nanowire–based GAA TFET (top right), and MOSFET–like CNFET (bottom)......... 99 Figure 43 Schematic of an InAs nanowire–based GAA p–type TFET and the corresponding band diagram in the OFF/ON states (left), same information for an n–type TFET (right)................. 100 Figure 44 ID –VGS curve of a p–type TFET for various nanowire diameters and carrier effective masses. Higher currents are achieved at smaller nanowire dimensions due to enhanced gate control. Smaller effective masses increase the tunneling probability; hence offer larger current values............................... 102