« WIRELESS PARYLENE-BASED RETINAL IMPLANT Thesis by Jay Han-Chieh Chang In Partial Fulfillment of the Requirements for the Degree of Doctor of ...»
1.3 Parylene Parylene is the trade name for members of a unique family of plastic polymers which are deposited by the dimer of para-xylylene (di-para-xylylene, or DPXN) . It was first discovered by Dr. Michael Mojzesz Szwarc at the University of Manchester, England, in 1947 and commercialized by Union Carbide Corporation in 1965 . Parylene is used in various industries because of its many excellent properties. Among them, the major application is in the electronics industry for the application on the printed circuit board (PCB) coating. Here, parylene protects the electronic devices against damages from moisture and corrosive etchants. Figure 1.11 shows the chemical structures of the three most commonly used parylene types: parylene-N, parylene-C, and parylene-D. A new parylene variant, which is called parylene-HT is also demonstrated here. In which, parylene-N is poly-para-xylylene, a completely linear and highly crystalline polymer; parylene-C is essentially parylene-N with a chlorine atom replacing one of the aromatic hydrogens; parylene-D is very similar to parylene-C, but with two aromatic hydrogens being replaced with chlorine atoms. The benzene backbone of the parylene family makes them very chemically inert. At the same time, the polyethylene-like interconnect makes them flexible. More detailed electrical, mechanical, thermal,
Chemical structure of Parylene-N, -C, -D, and-HT and the process temperature.
A list of selected properties of parylene-N, -C, -D and -HT is shown in Table 1.1. Parylene exhibits outstanding mechanical strength and flexibility as a thin film coating. With Young’s modulus of around 4 GPa (similar to Nylon) and an elongation-to-break percentage of more than 200%, parylene-C is a perfect membrane material on bio-MEMS applications.
Besides, parylene is also an excellent electrical insulator with high electrical resistivity. For example, the breakdown voltage for 1 μm thick parylene is over 200 volts. Because the parylene film is highly conformal and pinhole free, it is also an excellent barrier to gas and moisture with moderate thickness. In addition, parylene is extremely inert to many chemicals and solvents. Based on the manufacturer’s study, solvents have a minor swelling effect on parylene-N, -C, and -D, with a 3% maximum increase in film thickness. The swelling is found to be completely reversible after the solvents are removed by vacuum drying. Inorganic reagents, except for oxidizing agents at elevated temperatures, have little effect on parylene. Optically, parylene is transparent in the visible light range. It only absorbs light under 280 nm in wavelength, which unfortunately limits its UV applications. Due to their slightly different chemical structures, the four types of parylene also differ in properties. Parylene-N has very good gap penetration characteristics. However, parylene-N also has the slowest deposition rate. Parylene-D can withstand higher temperature than parylene-C.
Parylene-C has a useful combination of electrical and physical properties, plus a very low
faster than that of the other two. Parylene-C is hence the better choice for most traditional biomedical applications. Parylene-HT is the new variant, and is expected to be a good prospect with its better thermal stability, improved electrical properties, increased UV stability, better crevice penetration, lower coefficient of friction, and better barrier properties ; it is also ISO 10993 biocompatible [24-26].
The parylene deposition process, called Gorham process , and the involved chemical processes are illustrated in Figure 1.12. The process starts with placing parylene dimer (di-paraxylylene), a stable compound in granular form, into the vaporizer, and the substrate to be coated into the deposition chamber. The whole system is pumped down to medium vacuum. The dimer is then heated in the vaporizer and sublimes into vapor at around 180 °C. The dimer vapor enters the pyrolysis furnace, controled at 690 °C, where the parylene dimers are dissembled into identical monomers (para-xylylene). In the room-temperature deposition chamber, the monomers reunite on all exposed surfaces in the form of polymers (poly-(para-xylylene)). The deposition takes place at the molecular level. The monomers are extremely active molecules which have a mean free path on the order of 1 mm (under deposition pressure of around 100 mTorr), resulting in superior penetration ability and a high degree of conformability to the exposed surfaces. Also, the coated substrate temperature never increases more than a few degrees beyond ambient temperature. Additional components of the parylene coating system include a mechanical vacuum pump and associated cold trap for pressure control. The process of parylene-C is almost identical to all four types of parylene, except for some minor differences in the setting of pyrolysis temperature and deposition pressure.
Typical deposition thickness ranges from five to tens of microns. It can also be deposited as thin as hundreds of angstroms as a semi-permeable structure for the application on filters. The deposition thickness can be controlled by the amount of dimer placed in the vaporizer. The normal deposition rate of parylene- C is about 3 μm per hour. It is directly proportional to the square of the monomer
together with a third metal which usually has a much lower melting temperature compared to the other two metals that need to be connected together. In addition to the physical reaction, there is also a chemical reaction happened in the soldering bonding process. Soldering bonding process is mainly applied to create a convenient and fast joint to make a good electrical contact between two separate metals. Solders typically do not provide very high mechanical strength because of the soft nature of popular solder materials. Soldering process is used extensively in the electronics industry for discrete components connected with printed circuit boards (PCBs). Its advantage is the easy application for quick and dirty bonding of discrete components with PCBs for bench testing, but the physical weakness of the solder bonding, toxicity of the materials, local heat problem necessary for bonding, and its inability to connect small and dense array pads makes soldering a less attractive choice than
Wire Bonding Wire bonding, as shown in Figure 1.14, is a process used to connect an on-chip pad and a substrate pad with a fine conducting wire. This substrate may be another chip or the bonding pads on PCBs. Popular materials for wire bonding include gold (Au) and aluminum (Al). The main advantage of wire bonding technology is the low-cost characteristics. However, the disadvantages include the requirements of larger bonding pads with size of around 100 × 100 µm2, and larger bonding pitch with size of around 200 µm. Besides, wire bonding requires large quantities of gold. It also has lower production rate, relatively poor electrical performance, and variations in bonding geometry. The robustness and reliability are also serious issues. In addition, it cannot be used on flexible PCBs for implant application since the wire bonder can easily damage the flexible substrates.
To date, the most advanced wire bonders can achieve up to around 14 wires per second.
Therefore, it remains more competitive than flip chip bonding for up to 500 I/Os per chip. The
Flip Chip Flip chip bonding technique, as shown in Figure 1.15, is developed to make electrical connection between the face-down components onto substrates, carriers, and PCBs by solder bumps on the chip bonding pads. Since wire bonding, the older technology which is gradually replaced by flip chip, uses face-up chips with a fine wire connection to each pad, therefore, the huge impedance contributed by the fine and long wire might be an issue. However, in flip chip, the interconnect length between the chip and the substrate is much shorter, and thus the impedance of interconnect is well controlled to be smaller. This is part of the reason that flip chip is applied in high clock speed
connecting all I/Os in a single process step. Besides, the solder bumps can be placed over the whole chip surface, which implies the ability to make connections to the chip with significantly higher I/O density. This advantage allows additional power and ground connection, which is possible to further increase the electrical performance.
While the flip chip bonding technique benefits the devices with high performance, its high cost is still the main challenge and limitation for main stream applications. Thus, much effort and attention continues to be made to reduce the costs. Besides, the toxic joint materials, solder bumps, are totally not desirable for implantable devices. Additionally, the global heating needed during bonding process also limits its application on some substrates which cannot stand at high temperatures.
1.4.2 State-of-the-art Chip Integration Technology 126.96.36.199 Microflex Microflex (MFI) is a new three-dimensional (3D) interconnect technique developed by the Fraunhofer Institute for Biomedical Engineering in Germany. Meyer et al.  utilizes a polyimide based multiple strand flexible ribbon cable with a photolithography patterned double metallization
correspond to the bonding pads on the chip. The via-hole of the contact pads on the ribbon cable is then filled with metal balls or wedges applied by a commercial wire bonder. The metal pair is welded and results in a mechanically stable and electrically reliable contact. This technology, though derived from the common wire bonding technology, is specifically designed and developed to integrate the passive and active electronic components to the electrodes, as shown in Figure 1.16.
The applied materials, such as polyimide substrate, platinum, and irridium, in this technology showed an excellent biocompatibility during in vitro and in vivo testing. In addition, this substrate has also proved to be non-cytotoxic according to the international standard DIN EN ISO 10993. Also, in chronic implantations in the sciatic nerve of rats and on the retina of rabbits, they caused no significant tissue reactions or alterations. The Microflex technology can also be applied to threedimensional (3D) structures and the density is comparable to that of the flip chip technology. Several ultrasound array sensors, retinal stimulators (EPIRET), and multiplexer modules have been integrated successfully with this technology [32–35].
The current device, EPIRET 3, has transmitting coils on external glasses and an internal receiver coil and chip secured in the eye in place of the lens, as shown in Figure 1.17. It can transfer energy and data from the external power source to the implant. Based on the design of epiretinal prosthesis, the stimulator was placed slightly inferior to the fovea and fixed with retinal tacks. In an exploratory human trial in 2009, the device was implanted for four weeks to observe the safety of the device and how well it would work. There was mild inflammatory response in some of the six patients which were treatable by local antibiotic and steroids, but they decided there was no lasting damage from the prosthesis. Four of the six patients gained light perception, one gained hand movement, and one had no light perception . However, more clinical trials are still needed to demonstrate the long-term biocompatibility. Besides, the mechanical properties of the bond on the substrate have yet to be tested as well. In addition, its tedious and low yield process also makes it difficult and costly to
Final implant with parylene C and silicone rubber encapsulation .
188.8.131.52 Boston Retinal Implant Project Dr. Wyatt and Dr. Rizzo from Massachusetts Institute of Technology developed a subretinal implant device aiming to achieve the goal of visual prosthesis . This device is also based on the polyimide substrate. The host flexible circuit was made by defining the metal trace with width of 50
prosthesis components were then assembled on the host polyimide substrate. Because the period for the animal surgical implantation trials was limited, these traces were fabricated from a Cu/Ni/Au metallization which were commonly used in industry for microelectronics. Besides, the coils were fabricated from Cu wire. Standard surface-mounted components were used for all the off-chip power supply parts, and these were assembled on the flex circuit substrate using conventional wave soldering techniques. The ASICs were mounted by stud bumping with 75-µm-high Au bumps, followed by flip-chip die attachment to the host substrate. The stud bumping was also used for the flex-to-flex connections between the flex circuits and the electrode arrays.
Although this device has gone through several in vivo studies, the integration approach proved to be prone to reliability problems. Also, the encapsulation coating by PDMS has less reliable
184.108.40.206 California Institute of Technology—CL-I2 Rodger and Li et al., have developed a chip level integrated interconnect (CL-I2) and further extended to an embedded chip integration technology and successfully demonstrated by integrating the flexible polymer (parylene) substrate RF coil with commercially available IC chips and other passive discrete components [38-39]. Figure 1.19 illustrates the conceptual schematic of this
carrier silicon wafer and directly integrated with an MEA and with, ultimately RF coil power and data connections. Finally, all the components will be further sealed with a parylene coating.
The cavity matching the chip dimension is first etched on the parylene-on-silicon substrate for chip placement by DRIE. After the chip is dropped into the cavity, parylene deposition is performed again to seal the chip and serve as the insulation between two metal layers. Then, the metal is deposited and a photolithography step is done to make the electrical connection between the pads on the chip and the other pads on outside components. The structure is finally released by back etching of the silicon substrate.