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«FLEXIBLE NEURAL IMPLANTS Thesis by Ray Kui-Jui Huang In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy CALIFORNIA ...»

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FLEXIBLE NEURAL IMPLANTS

Thesis by

Ray Kui-Jui Huang

In Partial Fulfillment of the Requirements

for the Degree of

Doctor of Philosophy

CALIFORNIA INSTITUTE OF TECHNOLOGY

Pasadena, California

(Defended June 25, 2010)

ii

© 2011

Ray Kui-Jui Huang

All Rights Reserved

iii

To My Family and Friends

iv

ACKNOWLEDGEMENTS

This dissertation not only reflects the countless hours spinning photoresist, cleaning parylene machines, and mixing epoxy in Caltech Micromachining Laboratory, but it is also a conglomeration of years of wonderful experiences, opportunities, lessons, and valuable encounters during my PhD career. This endeavor would not be possible if it were not for my families, my friends, my mentors, my colleagues, and all those whom I have met over the past years.

Coming to Caltech was one of the best decisions I have made. The lab was not just a research lab to publish papers, it was also a place to nurture students to be ethical, logical engineers; it was a shelter to develop a fearless mind and become a hands-on researcher; and most important of all, it was a sanctuary to foster good thinkers who can solve any problem that they encounter. I have learned so much beyond what was written in books and papers, and I would not have been able to do so if I were not in this lab.

Dr. Tai, you have taught me so much; not just about how to be a good scientist, but you have guided me on acquiring a positive and forward-thinking attitude that has encouraged me and supported me through the toughest time. I want to express my sincerest gratitude and appreciation to you; thank you for the advice, the leadership, the support, and having faith in me. It was my honor to have you as my advisor.

To members of the Caltech Micromachining Laboratory, in particular Dr.

Changlin Pang, Dr. Wen Li, Dr. Damien Rodger, Dr. Po-Jui Chen, Dr. Jason Shih, Dr.

Siyang Zheng, Dr. Mike Liu, Dr. Nick Lo, and Dr. Quoc Quach; thank you for mentoring and training me the during the earlier years of my career in the lab. To the rest of the v members, Dr. John Chen, Luca Giacchino, Jeffrey Chun-Hui Lin, Mandheerej Nandra, Justin Young-Hyun Kim, Bo Lu, Penvipha Satsanarukkit, Wendian Shi, Han-Chieh Chang, Yu Zhao, Charles Deboer, Zhao Liu and Dongyang Kang, thank you for your support, generous assistance and brilliant ideas. The lab would not have been this organized and efficient if it were not for the collaboration and hard work from each and every one of you. Thanks to the very helpful students Adi Gani, Suyao Ji and Siripat Sumanaphan for your hard work.

My thanks also go to Christine Garske, Agnes Tong and Tanya Owen, thank you for your help in purchasing and administrative tasks. You have made the life of all members in the lab so much easier and smoother. Thanks to Mr. Trevor Roper, without whom we would not have any device we have made to date.

I also want to give credit and my appreciation to Dr. James Weiland and Dr. Ellis Meng, and USC students including Artin Petrossians, Alice Cho, Lauren Hickey, Christian Gutierrez, Dr. Brian Li and Dr. Ronalee Lo, who have dedicated their time and effort in advancing the research program in both USC and Caltech and have helped me tremendously in my research endeavor in BMES ERC.

Special thanks go to all the friends that I have made and the old friends that I am so lucky to have kept in contact with during all these years. You have kept me company, brought me laughter, taught me lessons and made my life more exciting and fulfilling than I ever could have imagined. Special note to my Cornell buddies, Caltech ACT members and Sweet Pepper fans, you have been there for me through my highs and lows,

–  –  –

brother who have always been there for me and have given me unconditional support over the years in every aspect of my life. Words cannot simply describe my sincerest gratitude and appreciation to them. Thank you.

–  –  –

Despite recent development in integration technologies for biomedical implantable devices, current state-of-the-art prosthetic platforms still lack a reliable and convenient packaging scheme to integrate high-density signal-driving chips, wireless telemetry circuitries and noise-canceling amplifiers, mainly due to the limitations in fabrication technology, material compatibility and interconnect reliability. In this dissertation, new packaging technologies are developed and presented to enable a new generation of flexible neural implants. These technologies can also house integrated circuit chips and provide high-density electrical connection to it.

This packaging scheme utilizes the parylene-metal-parylene skin structure and can be totally integrated and be monolithically fabricated with existing functional devices. The size and the electrode patterns can be modified to suit different chips and applications.

Integration with flexible cable integrated silicon probes for neural prosthesis, implantable muscle stimulators and implantable RFID tagging technology are all successfully demonstrated in this dissertation. Other discrete components can also be integrated to achieve high level functionality.





In order to ensure the long-term stability of such packaging scheme, accelerated hot saline soaking test is conducted on the overall structure and its components. Detailed adhesion enhancement techniques are also presented to improve its performances. A physical model of the flexible retinal implant is then tested in vivo during the course of the experiment. Finally, the high-density squeegee bonding technique is introduced, which

–  –  –

Acknowledgements

Abstract

Table of contents

List of figures

List of tables

Glossary

1 INTRODUCTION

1.1 PROSTHETIC APPLICATIONS—THE NEED AND DRIVING FORCE

1.1.1 Retinal Prosthesis

1.1.2 Neural Prosthesis

1.2 INTEGRATION TECHNOLOGY

1.2.1 Traditional Chip Integration Technology

1.2.2 State-of-the-Art Chip Integration Technologies with Biodevices

1.3 PROBLEMS AND CHALLENGES

1.4 MEMS TECHNOLOGY

1.4.1 Bulk Micromachining

1.4.2 Surface Micromachining

1.4.3 Introduction to Parylene

1.4.4 Parylene for MEMS and Biomedical Applications

1.5 PROSTHETIC INTERFACE TECHNOLOGY THRUST

1.6 LAYOUT OF THE DISSERTATION

1.7 SUMMARY

2 PARYLENE POCKET TECHNOLOGY

2.1 INTRODUCTION

2.2 POCKET DESIGN—PARYLENE VS. SILICON SUBSTRATE

2.3 FABRICATION

2.3.1 First Generation

2.3.2 Second Generation—Silicon Substrate

2.3.3 Second Generation—Parylene Substrate

2.3.4 Variety of Pockets

x 2.3.4.1 For IC Chips

2.3.4.2 For Discrete Components

2.3.4.3 For Double Side and Multiple Layer Components

2.4 INTEGRATION WITH SILICON PROBES

2.4.1 Design

2.4.2 Fabrication

2.4.3 Testing and Verification

2.5 SUMMARY

3 IMPLANTABLE CHIP INTEGRATION TECHNOLOGY

3.1 INTRODUCTION

3.2 RFID CHIP INTEGRATION

3.2.1 Design and Fabrication

3.2.2 Integration Demonstration

3.2.3 Functional System Testing

3.3 BION CHIP INTEGRATION

3.3.1 Design and Fabrication

3.3.2 System Integration Demonstration

3.3.3 Functional System Testing

3.4 CONCLUSION

4 PACKAGING, ACCELERATED LIFETIME TESTING AND MODELING. 71

4.1 INTRODUCTION

4.2 PARYLENE TO SILICON INTERFACIAL ADHESION ENHANCEMENT

4.2.1 Sample Preparation

4.2.2 Experiments

4.2.2.1 Partial Film Peeling Test

4.2.2.2 ASTM Standard Tape Peeling Test

4.2.2.3 Accelerated Soaking Tests

4.2.2.4 HF Soaking Tests

4.2.2.5 Conclusion

4.3 ACCELERATED LIFETIME SOAKING TEST OF PROTECTED ICS

4.3.1 Samples Preparation

4.3.2 Passive Soaking

4.3.3 Diffusion of Electrolyte in Silicone

xi 4.3.4 Active Soaking

4.3.5 Conductive Epoxy

4.4 MECHANICAL MODEL FOR IMPLANTATION STUDIES

4.4.1 First Version Mechanical Model

4.4.2 Second Version Mechanical Model

4.4.3 Discussion

4.5 CONCLUSION

5 HIGH DENSITY CHIP INTEGRATION

5.1 INTRODUCTION

5.2 PARYLENE POCKET ON SILICON SUBSTRATE

5.2.1 Fabrication

5.2.2 Fabrication Challenges

5.2.2.1 Lift-off Metal Patterning

5.2.2.2 Thick Photoresist for Plasma Etching

5.2.2.3 Parylene Cracking

5.2.2.4 Metal Line over a Step

5.2.2.5 Pocket Size

5.3 PARYLENE POCKET ON PARYLENE SUBSTRATE

5.3.1 High Density Integration

5.3.1.1 Alignment

5.3.1.2 Squeegee Technique

5.3.2 Integration Issues

5.3.2.1 Metal Pad on Edge

5.3.3 Repairs and Enhancements

5.3.3.1 Laser Fix (Short Circuit)

5.3.3.2 Conductive Epoxy Failures

5.4 FUNCTIONAL TESTING

5.5 CONCLUSION

6 CONCLUSION

BIBLIOGRAPHY

 xii

–  –  –

Figure 1.1.

Soldering a component onto the back of a printed circuit board.

Figure 1.2.

Gold wire bonded onto metal pads to make electrical connections................. 5 Figure 1.3. Illustration of the ball grid array; the BGA on an actual IC chip.

Figure 1.4.

The Michigan three-dimensional neural probe array [40]; SEM picture of the tip of the Michigan probe [33].

Figure 1.5.

Concept of embedded chip integration; overall view of the device; close-up view of the embedded chip; close-up view of the coil wires.

Figure 1.6.

Close-up picture of the MicroFlex bonding technique, facilitated by a commercial wire bonding machine setup [70].

Figure 1.7.

Final implant with parylene C and silicone rubber encapsulation [71].......... 10 Figure 1.8. Schematic representation of the retinal implant by Theogarajan et al. [73]... 11 Figure 1.9. (a) Schematic of the three-dimensional stacked chip [74]; (b) implantable sensor system: A control unit and analogue part with RF coil [75].

Figure 1.10.

Comparison of positive and negative photoresist

Figure 1.11.

Comparison of surface micromachining and bulk micromachining............ 17 Figure 1.12.

Comparison of isotropic and anisotropic wet etching and dry etching........ 18 Figure 1.13.

Examples of silicon bulk micromachining; the substrate material is etched away to create different features [81].

Figure 1.14.

An example of surface micromachined gears [82].

Figure 1.15.

Chemical structures of parylene N, C, D, and HT, and some of the correlated process parameters used in parylene deposition system PDS 2010 and 2060........... 21 Figure 1.16.

Parylene deposition system and its deposition process.

Figure 1.17.

Permeability vs. time of different materials.

Figure 1.18.

Proposed all-intraocular system for high density epiretinal implant............ 27

–  –  –

Figure 2.2.

Conduction chip and the CMOS amplifier chip used in the testing of the devices. The conduction chip was made in-house with electron beam evapoator metal deposition on oxide wafer and DRIE process.

Figure 2.3.

Process steps for parylene pocket with silicon substrate. The entire pocket structure can be released from the wafer by DRIE or wafer dicing.

Figure 2.4.

The first-generation parylene pocket with one opening on the side; all bonding pads are located on the chip.

Figure 2.5.

Issues during fabrication and chip insertion; (a) chip insertion tearing the side of the pocket, causing breakage of the parylene; (b) open circuits in trace lines; (c) the parylene substrate is stuck on the surface of the silicon substrate; (d) delamination of the parylene pocket from the silicon substrate.

Figure 2.6.

Insertion of the IC chip into the parylene pocket; tweezers are used to align the bonding pads to the metal pads on the chip under the microscope.

Figure 2.7.

Alignment of the pads on the parylene pocket and the metal lines on the inserted chip. The alignment offset was on the order of 10 to 20 μm; a drop of biocompatible conductive epoxy is applied over the metal pads to provide electrical conduction. The size of the drop is on the order of 150 to 200 μm.

Figure 2.8.

Bonding scheme for the parylene pocket. A drop of conductive epoxy is applied on the bonding hole that exposes the metal pads on the IC chip underneath. 36 Figure 2.9.

Fabrication process for the pocket structure with parylene C substrate. The device can be made on any type of wafer.

Figure 2.10.

Parylene pocket-only structure. This device is used to test the amplifier chip after bonding. Signal is driven in from the bonding pads on the right-hand side of the figure and is measured from the bonding pads on the left-hand side of the figure.... 39 Figure 2.11.

Parylene pocket-only structure. It is used to test the amplifier chip after bonding. Signal is driven in from the bonding pads of the parylene structure on the right-hand side of the figure.

Figure 2.12.

Input of 5 mV (10 mV peak to peak) sine wave of 1 kHz is passed into the amplifier (gain = 60) and its oscilloscope output is recorded. Signals of 0.5, 2, and 5 kHz were also tested with the chip.



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