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«SUBMICRON TECHNOLOGIES By Vijay Benakanakere Sheshadri Thesis Submitted to the Faculty of the Graduate School of Vanderbilt University in partial ...»

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UPSET TRENDS IN FLIP-FLOP DESIGNS AT DEEP

SUBMICRON TECHNOLOGIES

By

Vijay Benakanakere Sheshadri

Thesis

Submitted to the Faculty of the

Graduate School of Vanderbilt University

in partial fulfillment of the requirements

for the degree of

MASTER OF SCIENCE

in

Electrical Engineering

December, 2010

Nashville, Tennessee

Approved:

Professor Bharat L Bhuva Professor Robert Reed

ACKNOWLEDGEMENTS

I would like to thank my advisor Professor Bharat Bhuva, Professors Robert Reed and Ron Schrimpf for their guidance and encouragement without which this work would not have been possible. I would also like to thank Kevin Warren, Brian Seirawski and Nathaniel Dodds for many enlightening discussions and support during the MRED simulations. I am also grateful to Nelson Gaspard for his assistance in becoming acquainted with TCAD. I want to thank all my fellow students in the Radiation Effects and Reliability Group for all the timely help and advice. Lastly I thank my loving parents and my friends for their emotional support throughout all my ups and downs.

ii  

TABLE OF CONTENTS

ACKNOWLEDGEMENTS…………………………………………………………….... ii LIST OF FIGURES……………………………………………………………………... iv Chapter Page I.   INTRODUCTION TO SEE

II.   BACKGROUND ON SEE&SCALING

Qcrit scaling

SER scaling

Charge sharing

  III.   CRITICAL CHARGE TRENDS

Flip-flop designs

SEU due to single-node charge collection

SEU due to multiple-node charge collection

  IV.   MONTE CARLO SIMULATIONS

Construction of the flip-flop models

MRED Simulations

Simulation results

  V.   SUMMARY

APPENDIX

REFERENCES

         

1. A particle strike generating electron-hole pairs in the device

2. Basic classification of Single-event effects

3. An illustration showing latching of a transient pulse

4. Qcrit of latches and SRAM

5. Impact of technology scaling on Soft error rate of flip-flops

6. Illustration showing nodal separation between two devices, charge sharing between transistors

 

7. Variation of MBU probability with inter-cell (C-C) distance

8. MS DFF, one stage of the DICE flip-flop and 8T storage cell of Q8FF

9. Sensitive nodes and vulnerable transistors in one stage of the DFF and shape of the current source

 

10. Sensitive nodes and vulnerable transistors of Q8FF

11. Qcrit for one stage of DFF, LPFF and Q8FF

12.Sensitive pairs of a DICE latch, critical charge combinations for all the sensitive pairs of DICE and position of sensitive nodes on the layout of DICE latch

 

13. Charge threshold plot indicating the upset boundary

14. Critical charge combinations for most vulnerable node pairs of DFF, DICE, LPFF and Q8FF

 

15. Comparison of all the designs at 90nm, 65nm and 45nm technology node............... 17  

16. Illustration of a conceptual transistor representing the sensitive drain by a nested sensitive volume group

–  –  –

18. The Qcoll plotted as a function of the distance between strike location and the drain of the transistors

 

19. Defining sensitive volumes for the PMOS transistors using the TCAD charge collection data

 

20. Data fit obtained with the least squares method for the transistors

21. The positioning of the sensitive nodes on the flip-flop layout of DFF, DICE and Q8FF and the sensitive volume group for each transistor

 

22. A conceptual drawing of the scaling of sensitive volumes

23. The charge threshold curve for DFF designed at 90nm process is fitted to a parabolic equation

 

24. Illustration of the Δ margin concept for defining single-node upsets

25. The normalized cross-section for multi-node upsets in DICE

26. Normalized single and multi-node cross-sections for DFF, LPFF and Q8FF............ 29  

27. The layout of Q8FF with the three sensitive node pairs.

28. Comaprison between normal and grazing angle of incidence ………………………31

29. The effect of varying Δ margin on single-node upset cross-section for DFF, LPFF and Q8FF.

 

30. Comaprison between double exponential and TCAD current source

31. Comaprison between well contacing schemes

Table I. Power and delay of the flip-flops normalized w.r.t DFF…………………………9 Table II. Variation in upset cross-sections of the flip-flops normalized w.r.t the 90nm model

                Single-event effects (SEE) in microelectronics are caused when highly energetic particles pass through a semiconductor material creating electron-hole pairs (EHPs) (figure 1) along its strike path until it has lost all its energy or left the semiconductor. The particle strike may cause a soft-error (e.g. transient disruption of circuit operation, change of logic state) or even permanent damage to the device (hard-error), based on factors such as circuit topology and amount of charge collected. [1, 2] Figure 1: A particle strike generating electron-hole pairs in the device. [3]     In case of the soft-error, the SE results in data corruption while the device remains intact. Hence, the erroneous data can be corrected by writing new data. On the other

–  –  –





(SE) at a node in an integrated circuit. Under certain conditions, this transient pulse can propagate through the integrated circuit and eventually appear at the circuit’s output. It may also be captured if it appears at the input of the latch during the setup and hold time of the latch (also known as window of vulnerability). A SET, thus captured, becomes a single event upset (SEU) (figure 3). [5]

–  –  –

There are various soft-error mitigation techniques that can be implemented at the device, circuit and architecture levels. For instance, triple-well and silicon-on-insulator technologies are effective mitigation strategies at the device level, Triple Mode Redundancy (TMR) [7] and Dual Interlocked Cell (DICE) [8] are mitigation techniques at the circuit-level whereas error correcting codes (ECC) and redundant execution are some of the soft-error mitigation schemes at the architecture-level.

–  –  –

  Advances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in rapidly shrinking technology node and aggressive scaling of voltage. This has resulted in an increase in the probability of soft-errors in advanced CMOS digital logic circuits.

In most modern microprocessors large memory arrays such as caches or register files are protected Error detection and correction (EDAC) schemes. As a result, the chip level soft error rates (SER) are dominated by the error rates of the flip-flops in the microprocessor. [9] Qcrit scaling The critical charges of the sequential nodes approximately scale according to

–  –  –

is known to decrease both Vcc and C. Hence, Qcrit is also expected to decrease as a result of technology scaling [9] and is a cause of concern as technology advances into nanometer technology (figure 4). Trends in Qcrit scaling for flip-flops will be revisited in Chapter 3.

SER scaling

–  –  –

where Adiff is the sensitive drain diffusion area, Qcrit is the critical charge, κ denotes an overall scaling factor and η is the charge collection efficiency[11, 12]. Technology € scaling affects factors governing the SER such as the sensitive drain diffusion area, Adiff, and the critical charge, Qcrit. Since scaling reduces both Qcrit and the efficiency, η, there have been inconsistencies concerning the experimental data on SER for latches / flip-flop in some of previous research in this area, as illustrated in figure 5. These inconsistencies can be attributed to the variation is the design of the latch considered in each of these experiments.

Figure 5: Impact of technology scaling on Soft error rate of flip-flops [9, 12]

–  –  –

Figure 6: Illustration showing (a) nodal separation between two devices (b) charge sharing between two PMOS devices (c) charge sharing between two NMOS devices [13]   Decreasing technology feature size has resulted in higher packing densities. As a result of this, charge generated by a single particle strike may be collected at multiple nodes [14].

This multiple node charge collection may have an increasing impact on the vulnerability of the circuit to single-events as devices are scaled down. Charge sharing studies by Amusan et al showed that the main mechanism for charge sharing in PMOS devices is the parasitic bipolar transistor; while in the case of NMOS devices it is diffusion. [13]

–  –  –

bit maybe affected, creating a multi-bit upset (MBU). Decreasing feature sizes have resulted in smaller cell sizes in SRAM and hence the probability of MBU is increasing as shown in figure 7.

Figure 7: Probability of MBU increases as inter-cell (C-C) distance reduces [9] Mitigating SEU will become more complex as many traditional design approaches to mitigate soft errors, such as the DICE, are based on the assumption that an incident particle affects only one circuit node. The DICE latch has been shown to be vulnerable to SEU at low LET when multiple nodes of the latch collect charge. [15] This work focuses on investigating the effects of Qcrit scaling and multi-node charge collection on the SER trend, keeping the design geometry constant across the technology nodes considered. Chapter III of the thesis discusses the trends in critical charge for

–  –  –

the Monte Carlo simulations that have been carried out in order to study the probability of upsets in the flip-flop and how technology scaling affects this probability.

–  –  –

Four different flip-flop designs with varying levels of area, power, speed, and softerror hardness were considered for this study. The flip-flops designs, as shown in figure

–  –  –

The MS DFF has two storage nodes each stage, which form a complimentary pair. The LPFF has the same number of storage nodes as the DFF. The DICE design consists of cross-coupled inverters. Each stage of the design has four storage nodes, two of which are redundant. A voltage transient on one storage node requires a large amount of time to propagate through the remaining three storage nodes and as a result, the three storage

–  –  –

The Q8FF also, same as DICE, has four storage nodes per stage including two redundant nodes. However, the Q8FF is coupled differently than the DICE flip-flop. The power and delay of the flip-flops, normalized with respect to the DFF for each technology node considered, are given in Table 1. The max. C-Q delay refers to the clock to Q delay in the flip-flops and is the maximum delay observed over both stages of the flip-flop and both states of the data (i.e., Data = HIGH and Data = LOW).

–  –  –

Circuit-level simulations of the designs were carried out using Cadence® Virtuoso® Spectre® Circuit Simulator tool [16]. The Spectre® Circuit Simulator provides accurate and detailed transistor-level SPICE-level analysis of analog and digital circuits.

The flip-flop designs were simulated in three different technologies, namely IBM 90nm, IBM 65nm and TSMC 45nm technologies. The FET model used in these PDK was BSIM4. Sensitive nodes in the flip-flop, upon sufficient charge collection (a.k.a. critical charge), will cause the circuit to erroneously flip its state. To identify such sensitive nodes and estimate their critical charge (Qcrit), charge was deposited on each node in the circuit by connecting a current source based on 3D TCAD simulations [17], to the node in consideration. The shape of the current pulse is illustrated in figure 9(a). The charge deposited on a node was varied until an upset was observed; the amount of charge for which an upset occurred is the Qcrit for that node. The sensitive nodes and the vulnerable transistors of one stage of the DFF for Data = ‘HIGH’ is shown in figure 9(b).

–  –  –

The sensitive nodes of Q8FF for Data = ‘HIGH’ and their Qcrit values are shown in figure

12. The DICE flip-flop, being a radiation-hardened design, did not show any upsets due to charge deposition on a single node for a large range of deposited charge. Figures 11 & 12 indicate that the critical charge decreases as technology scales. This is consistent with previous findings of [9, 10], already discussed in Chapter 2 of this thesis.

SEU due to multiple-node charge collection In deep sub-micrometer technologies, feature size scaling and high transistor packing densities has lead to reduced nodal charge and reduced spacing between transistors. Due to this, charge generated due to an ion strike can be collected at multiple nodes in a circuit [13, 14]. It has been shown by Amusan et al. [15] that charge collection by multiple nodes (a.k.a charge sharing) will lead to increased susceptibility of hardened flip-flop designs.

–  –  –

collection, causes the latch to upset. To simulate charge collection by two nodes, charge is deposited simultaneously on the node pairs using multiple current sources and varied to obtain a number of charge deposition combinations at which the flip-flops upset. As multi-node charge collection is a strong function of layout, and the layout may contain any of these nodes in physical proximity, all possible combinations of node pairs were simulated. The sensitive pairs in DICE latch are indicated in figure 12(a) and the corresponding charge combinations are represented as charge threshold plots in 12(b).

–  –  –



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